The invention relates to a sender device for sending digital information in the form of electrical binary signals to a receiver device. Said sender device comprises N-MOS transistors and P-MOS transistors. Each N-MOS transistor has an N-channel, and each P-MOS transistor has a P-channel.
Advances in electronic technology and design, and a strive towards boosted performance in terms of power consumption and speed, among many other things, has led to a variety of concepts for electrical binary signalling between circuits and circuit boards. Early concepts are DTL (Diode-Transistor Logic), TTL (Transistor-Transistor Logic) and ECL (Emitter Coupled Logic). These employ so called single-ended signalling. More recent concepts often employ a technique called differential signalling, also known as balanced signalling, which uses two signalling wires. Such concepts are DPECL (Differential Pseudo Emitter Coupled Logic), LVDS (Low Voltage Differential Signalling) and GLVDS (Grounded Low Voltage Differential Signalling). GLVDS is disclosed in the Swedish patent applications SE 9304025-1 and SE 9400971-9.
Although the above mentioned differential signalling concepts are indeed differential, each of the two signalling wires operate at fixed nominal voltages, which are related to ground. Each wire operates at two voltage levels, referred to as low voltage level and high voltage level, respectively.
DPECL typically has a signalling low voltage level of 3.4 V, and a high level of 3.9 V. LVDS on the other hand has a low level of 0.95 V, and a high level of 1.45 V, while GLVDS has a low level of 0 V and a high level of 0.5 V. The voltages are related to ground.
A sender device and a receiver device of a signalling concept of the above said types sends and receives, respectively, signals within a quite narrow voltage interval. In particular, a sender device and a receiver device for signalling at voltage potentials close to ground level, such as in GLVDS, typically operate only for low signalling voltage levels, e.g. less than 1 V. Such a sender device is not compatible with a receiver device of a different signalling concept that requires other signalling voltage levels.
A problem is to arrange electronic circuitry for a universal sender device which operates within a broad range of signalling voltage levels.
In U.S. Pat. No. 5,179,293 is disclosed a technique and circuit for switching a bipolar output stage between an active mode and an inhibit mode. In the inhibit mode, the output stage is deactivated, and the output node of the stage represents a high impedance.
In U.S. Pat. No. 5,319,259 is disclosed an output stage suitable for use with a variety of supply voltages, including supply voltages less than 5 volts. The output stage allows proper operation when a legitimate over voltage is applied to its output pad.
In U.S. Pat. No. 5,111,080 is disclosed a signal transmission circuit in which a signal is converted into two complementary signals which are output from a signal transmission circuit via series resistors. The amplitude of each of the complementary signals is reduced by the series resistors and terminating resistors provided on a signal receiving side. The signal receiving side shifts the level of its received input. The level shifted signals are amplified by a high-input impedance differential amplifying circuit.